1. IR @ Alliance University

Browsing by Author A G. Sasikala

Jump to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:  
Showing results 1 to 1 of 1
Issue DateTitleAuthor(s)
2014QCA Based Low Power Parallel Binary Adder/Subtractor Using Reversible Logic GatesA G. Sasikala; S. Maragatharaj
Showing results 1 to 1 of 1