Please use this identifier to cite or link to this item: https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/1354
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dc.contributor.authorDhariwal, Sandeep-
dc.date.accessioned2023-09-27T07:18:02Z-
dc.date.available2023-09-27T07:18:02Z-
dc.date.issued2020-10-10-
dc.identifier.urihttps://doi.org/10.23940/ijpe.20.03.p1.325332-
dc.identifier.urihttp://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/1354-
dc.description.abstractIn this work, different ring VCO topologies and architectures are designed to improve the performance of the conventional VCO structure. A single-ended ring VCO is designed and implemented at different control voltages. The output frequency range observed is between 3.27 and 12.57 GHz with the control voltage ranging from 1 V to 0.5 V. The minimum delay measured is 17.8 picoseconds. The other architecture involves the reverse substrate-bias (SB) technique and differential structure for further improvement of the performance parameters of the VCO. All the topologies are designed in Cadence Virtuoso with gpdk 90 nm technology. The differential structure and reverse SB structure result in frequency ranges of 17.405 GHz to 10.982 GHz and 11.87 GHz to 13.77 GHz, respectively. The results demonstrate a minimum delay, and the power consumptions are 8.1 picoseconds and 62.42 µW for the differential configuration and 8.27 picoseconds and 32.96 µW for the reverse-substrate bias technique, respectively. Overall, the voltage-controlled ring oscillator with reverse substrate bias is most suitable for delay reduction.en_US
dc.language.isoenen_US
dc.publisherTotemen_US
dc.subjectCadence Virtuosoen_US
dc.subjectpower consumptionen_US
dc.subjectdifferential configurationen_US
dc.subjectsubstrate biasen_US
dc.titleDelay Reduction by Implementation of Voltage-Controlled Ring Oscillator with Reverse Substrate Biasen_US
dc.typeArticleen_US
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