Design and Analysis of Power and Area Efficient Novel Concurrent Cellular Automation Logic Block Observer BIST Structure

Abstract

This paper presents a novel architecture named as Concurrent Cellular Automation Logic Block Observer (CCALBO) BIST structure. This technique is a combined result from the designs of CBILBO (Concurrent Built In Logic Block Observer) and CALBO (Cellular Automation Logic Block Observer). Architecture of designing the CCALBO cell and its fault masking probability with inclusion in a combination and sequential CUT has been considered. Vedic Multiplier and Multiply & Accumulate Unit (MAC) are used as circuit under test (CUT). CCALBO-based BIST is compared with most competitive technique CBILBO-based BIST. Major parameters such as power and area have been considered. Compared to CBILBO technique, CCALBO-based BIST has presented significant dynamic power reduction using Vedic multiplier and MAC unit as circuit under test (CUT). It has been observed that area also gets reduced in the novel CCALBO design, because parallel in parallel out (PIPO) registers are used to generate scan chains in test logic. CCALBO-based BIST has been found to achieve fault coverage of 100% in lesser duration as compared to CBILBO. Overall, CCALBO is better over CBILBO in the major aspects of area and low power dissipation and more reliable with respect to testing.