Novel Design Approach for Universal Shift Registers Using Reversible Logic

Abstract

Day by day new technologies are emerging to focus on reducing power, area and increasing the speed of operation. Reversible logic is an emerging technology in the field of low power computation. Shift registers are among the most important elements in fabricating reversible memory circuits and Arithmetic Logic units. In this paper, we represent efficient design of 4-bit and 8-bit reversible shift registers SIPO (Serial IN and Parallel Out), SISO (Serial IN and Serial Out), PIPO (Parallel IN and Parallel Out), PISO (Parallel IN and Out) and Universal Shift Registers (USR). Garbage reduction is achieved by the existing designs. All Shift Registers are built with ‘0’ garbage output (GO) and reduced constant inputs (CI). 4Bit SIPO is built with 3 CI and it is 62.5% improvement over the existing design. The same circuit does SISO functionality too. In this improvement of 25% in CI and 100% in GO is achieved. 4 Bit PIPO circuit is built with 3 CI and it is 25% improvement over existing design. The same circuit does PISO functionality too. The proposed design of SIPO, SISO and PIPO shift registers. 4 Bit PISO is built with 3 CI and 4 GO with an improvement of 60% and 70% respectively. 4-Bit universal shift register is built with 11 CI and 15 GI. CI of 4 bit USR is improved by 65.6% over one design and 50% over another design. GO of 4-bit USR is improved by 6.25% over one design and 53.1% over another design. The 8-bit shift registers of all configurations are built. © 2023, Scibulcom Ltd. All rights reserved.