A Modernistic Gate Clustering Technique to Depreciate Leakage in Cmos Circuits

Abstract

Low power design is one of the most emerging paradigms in VLSI industry, since it is much important for hand held portable applications. As modern VLSI design emerges based on nanometer technology, power dissipation has become an important design closure parameter in ultra low submicron digital designs. Moreover, in CMOS logic circuits, the sub-threshold leakage current increases due to reduction in threshold voltage and voltage scaling which is most responsible for leakage power dissipation during standby mode and are increasing dramatically for every technology generation. Nowadays, this static power dissipation becomes a critical factor in low power design due to emergent mobile products. It means, the leakage power dissipation should be a major problem and it’s a vital challenge for VLSI designers. In this paper, a new heuristic approach for clustering the logic gates in conventional CMOS design is proposed. Also, a power-gating scheme with the intention of diminishing leakage in idle mode is presented. The use of clustering will reduce the count of sleep transistor and the power gating helps more leakage savings in CMOS design. The proposed technique is tested on 4:1 multiplexer and 4 bit carry look ahead adder. Design and simulation were done on Tanner Tool 15.1 using CMOS nanometer technology.