Enhancing The Performance of Wallace Tree Multiplier At 45Nm Node Technology

Abstract

Multipliers are crucial components in VLSI circuits, performing the arithmetic operation of multiplication on binary numbers. They find applications in processors, digital signal processors and graphics processing units. The Wallace Tree Multiplier is a crucial component in many digital circuits, especially in high-speed and low power arithmetic units. This paper aims to give a power dissipation comparison between GDI (Gate Diffusion Input) based 4x4 Wallace tree multiplier and Adiabatic 4x4 Wallace tree multiplier. The simulation has been carried out by utilizing the Cadence virtuoso to simulate the proposed WTM design.