Parametric Analysis On Reliability and Degradation of 18Nm Finfet Sram

Abstract

The oxide thickness in CMOS technology has become increasingly challenging due to the rising demand for SRAM, particularly in System On-Chip applications. Leakage power significantly impacts the chip design process, along with considerations for SRAM speed and power consumption. Bias temperature instability (BTI) is a major reliability issue that affects the performance of both current and future semiconductor devices. This project provides a detailed analysis of the BTI impact on the time dependent degradation of FinFET-based SRAM cells. The SRAM cell designed in this study features single-ended write and read operations, which help to reduce overall power dissipation. Verification of the design was performed using Tanner EDA tools at the 18nm technology node, with power estimates comparable to those of a standard 6T SRAM block. The schematic was created using S-Edit, netlist simulation was carried out with T-Spice, and waveforms were observed in W-Edit. Notably, while previous technology utilized a 4x4 array, this design incorporates an 8x8 array, improving the performance and capacity of the SRAM cell.