Test Vector Optimization Using Pocofan-Poframe Partitioning

Abstract

This paper presents an automated POCOFAN-POFRAME algorithm that partitions large combinational digital VLSI circuits for pseudo exhaustive testing. In this paper, a simulation framework and partitioning technique are presented to guide VLSI circuits to work under with fewer test vectors in order to reduce testing time and to develop VLSI circuit designs. This framework utilizes two methods of partitioning Primary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning to determine number of test vectors in the circuit. The key role of partitioning is to identify reconvergent fanout branch pairs and the optimal value of primary input node N and fanout F partitioning using I-PIFAN algorithm. The number of reconvergent fanout and its locations are critical for testing of VLSI circuits and design for testability. Hence, their selection is crucial in order to optimize system performance and reliability. In the present work, the design constraints of the partitioned circuit considered for optimization includes critical path delay and test time. POCOFAN-POFRAME algorithm uses the parameters with optimal values of circuits maximum primary input cone size (N) and minimum fan-out value (F) to determine the number of test vectors, number of partitions and its locations. The ISCAS’85 benchmark circuits have been successfully partitioned, the test results of C499 shows 45% reduction in the test vectors and the experimental results are compared with other partitioning methods, our algorithm makes fewer test vectors.