Implementation of Reversible Logic Adder Circuits and Their Power Analysis

Abstract

In modern VLSI design, the device dimensions are shrinking(scaling) exponentially and the circuit complexity is growing exponentially. Device scaling is limited by the power dissipation, which in turn demand for better power optimization methods. This has led to the development of reversible circuits. The conventional digital circuits designed using basic logic gates AND, OR, EX-OR, NAND and NOR are not reversible. This work presents a literature survey on reversible circuits. Then few existing reversible gates like Feynman, Tofolli, Fredkin, Peres are implemented using Xilinx 12.3 tool. Subsequently half adder and full adder circuits are implemented using these gates. This work focuses on measuring the power consumption of all the implemented reversible circuits using Cadence Encounter RTL compiler tool. © Research India Publications.