Design and Analysis of 16-Bit Spares Kogge Stone Adder With Proposed 6T-Xor Cell, 1-Bit Hfa Design For High-Speed Arithmetic Operations

Abstract

As technology is growing widely, there is a vast demand for fast and accurate processing devices. Adder is the basic building to perform any arithmetic operations which depends on the efficiency of the XOR-gate design. Thereby, employed a proposed design comprising of 6T-XOR-cell, 1-bit Hybrid Full adder (HFA) design are implemented in a parallel prefix adder (PPA) which can be operated at a high speed computational environment such microprocessors, DSP-processors. To enhance the speed of operation and reduce the area occupying 16- bit spares kogge stone adder has been designed. This design needs less number of black-cells and gray cells and no need for buffer circuits compared to KSA. Typically, Buffer circuits are used in KSA to minimize the balancing effect during the speed of computation which has been sorted out during the implementation of this PPA design. The analysis and simulation result has been carried out for the proposed design by the cadence virtuoso in a 45nm node of supply voltage 0.8 V with 1GHz frequency. Power 0.42uW which is improved by 53%, Delay87.9 ps is improved by 46%, PDP is 41.08 (aj) is improved by 28% and transistor count is reduced from 24 to 16 compared to the existing hybrid full adder. © 2022 IEEE.