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https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/2256
Title: | Design and Analysis of Novel Xor/Xnor Based Hybrid Full Adder For Iot-Applications |
Authors: | Manchala, Venkata Subba Rao Sahoo, Satyajeeth Murthy, G Ramana |
Keywords: | Complementary-Metal Oxide Semiconductor (C-MOS) Hybrid Full Adder (HFA) Level-Restorer(LR) Transmission gate(TG) |
Issue Date: | 2022 |
Publisher: | 4th International Conference on Recent Trends in Computer Science and Technology, ICRTCST 2021 |
Citation: | pp. 445-450 |
Abstract: | This work deals with designing a novel XOR-cell for attain full swing voltage at high-speed operation. It is the basic building block for the design of any kind of full adder. The performance analysis and driving capability of the adder completely depend on XOR-cell only. Nevertheless, this XOR-cell is the major power consumption block in any kind of adder which achieves the full swing based on the CMOS-inverter and CMOS-Pass Transistor Logic (C-PTL). Hybrid Full Adder(HFA) is designed using three modules i.e XOR-cell, Transmission gate(TG), and Level restorer (LR). Among these three designs, TG-gate has a superior quality of achieving high-speed operation and low short circuit power. Performance parameters such as power, delay, Power-delay Product (PDP), Energy-delay product (EDP) are calculated and the simulation results are performed at a frequency of 1GHz in cadence virtuoso tool-45nm technology having a supply voltage (Vdd) of 0.8 V. This proposed Hybrid full adder is well suited for high-speed operation in IoT based-Applications. © 2022 IEEE. |
URI: | https://doi.org/10.1109/ICRTCST54752.2022.9781952 http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/2256 |
ISBN: | 9781665466332 |
Appears in Collections: | Conference Papers |
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