Design and Analysis of Low Power, Area Efficient Skip Logic For Cska Circuit In Arithmetic Unit

Abstract

The Processor cores of all the digital things have CPU with ALU as main block as a fact. Adder is the fundamental arithmetic component which performs considerable work. This article discusses the design, analysis of power optimized and area reduced Carry Skip Adder (CSKA). Area and Power are minimized with the help Hybrid GDI kind of MUX structure in skip logic of CSKA. The proposed one requires 39% low power consumption at the expense of 22% more delay than Transmission Gate (TG) based structure for skip logic. It's area in terms of cell count is negligibly smaller than CMOS MUX. © 2018 IEEE.