Comprehensive Study on The Signaling Schemes In on Chip Interconnects

Abstract

The continuous demand from the market for devices with more functionality per unit area may be met with aggressive improvement in scaling but have adverse effect on global interconnects thus having influence on delay as well as reducing system performance. The interconnect line drivers can be used to compensate the delay problem but its high dynamic power consumption to be taken care. One solution for this is to reduce Vdd but this can deteriorate the performance of the global interconnects line drivers unless low swing techniques are implemented. The low swing techniques suffer from increase in circuit complexity and large area usage. Also these techniques require additional circuitry like voltage generators and low-Vth devices. In an attempt to address these drawbacks, a new driver scheme has been designed, that has given improvement in terms of delay and power consumption, as well as noise immunity and leakage current. This paper gives a comparative study between the designed device and other drivers available. © 2018 IEEE.