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Please use this identifier to cite or link to this item: https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/2308
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dc.contributor.authorSooriamala, A P-
dc.contributor.authorThomas, Aby K-
dc.contributor.authorKorah, Reeba-
dc.date.accessioned2023-12-09T08:56:06Z-
dc.date.available2023-12-09T08:56:06Z-
dc.date.issued2021-
dc.identifier.citationpp. 330-334en_US
dc.identifier.isbn9781665440868-
dc.identifier.urihttps://doi.org/10.1109/WiSPNET51692.2021.9419476-
dc.identifier.urihttp://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/2308-
dc.description.abstractReversible logic is one of the latest technologies for low power design. This paper focuses on reducing the garbage output (GO) and constant input(CI) in combinational circuits. GO and CI are some of the parameters in Reversible logic. Two new reversible gates DINV (3*3) and TwinSJ (5*5) are designed. 3:8, 4:16 and 5:32 Decoders are the circuits built. Garbage output reduction of 25 to 66 percent is achieved. Also 12.5 to 75 percent reduction of constant input is achieved. © 2021 IEEE.en_US
dc.language.isoenen_US
dc.publisher2021 International Conference on Wireless Communications, Signal Processing and Networking, WiSPNET 2021en_US
dc.subjectCombinational circuitsen_US
dc.subjectConstant inputsen_US
dc.subjectDecoderen_US
dc.subjectGarbage outputsen_US
dc.subjectReversible logic circuitsen_US
dc.titleReduction of Garbage Outputs and Constant Inputs In Design of Combinational Circuits Using Reversible Logicen_US
dc.typeArticleen_US
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