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https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/2308| Title: | Reduction of Garbage Outputs and Constant Inputs In Design of Combinational Circuits Using Reversible Logic |
| Authors: | Sooriamala, A P Thomas, Aby K Korah, Reeba |
| Keywords: | Combinational circuits Constant inputs Decoder Garbage outputs Reversible logic circuits |
| Issue Date: | 2021 |
| Publisher: | 2021 International Conference on Wireless Communications, Signal Processing and Networking, WiSPNET 2021 |
| Citation: | pp. 330-334 |
| Abstract: | Reversible logic is one of the latest technologies for low power design. This paper focuses on reducing the garbage output (GO) and constant input(CI) in combinational circuits. GO and CI are some of the parameters in Reversible logic. Two new reversible gates DINV (3*3) and TwinSJ (5*5) are designed. 3:8, 4:16 and 5:32 Decoders are the circuits built. Garbage output reduction of 25 to 66 percent is achieved. Also 12.5 to 75 percent reduction of constant input is achieved. © 2021 IEEE. |
| URI: | https://doi.org/10.1109/WiSPNET51692.2021.9419476 http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/2308 |
| ISBN: | 9781665440868 |
| Appears in Collections: | Conference Papers |
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