Design and Study of Circuits Using Reversible Logic

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DC Field	Value	Language
dc.contributor.author	Sooriamala, A P	-
dc.contributor.author	Thomas, Aby K	-
dc.contributor.author	Korah, Reeba	-
dc.date.accessioned	2023-12-09T08:56:06Z	-
dc.date.available	2023-12-09T08:56:06Z	-
dc.date.issued	2021	-
dc.identifier.citation	pp. 213-217	en_US
dc.identifier.isbn	9781665428675	-
dc.identifier.uri	https://doi.org/10.1109/ICESC51422.2021.9532793	-
dc.identifier.uri	http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/2313	-
dc.description.abstract	In VLSI systems design, reversible Logic has gained importance for Reducing power. This paper focuses on designing of sequential circuits and reducing the number of constant inputs - CI and the garbage outputs - GO. Basic reversible gates are used to build sequential circuits. D Flip flop, Latch and RAM cell are developed. All circuits are VHDL coded on Xilinx tool, simulated and verified. Reduction in CI of more than 33 percent and GO of more than 80 percent is achieved. This is achieved by properly reusing the outputs for configuring the constant input of other gates. © 2021 IEEE.	en_US
dc.language.iso	en	en_US
dc.publisher	2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC)	en_US
dc.subject	CI	en_US
dc.subject	Flip Flop	en_US
dc.subject	GO	en_US
dc.subject	Latch	en_US
dc.subject	RAM cell	en_US
dc.subject	Reversible logic	en_US
dc.subject	Sequential circuits	en_US
dc.title	Design and Study of Circuits Using Reversible Logic	en_US
dc.type	Article	en_US
Appears in Collections:	Conference Papers

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