Design and Analysis of Low Power MAC for DSP Processor

Abstract

This research article represents low-power MAC architecture, which is one of the main building blocks of DSP processors. The MAC unit consists of three important blocks: a multiplier for multiplication, an adder for addition, and an accumulator for storing the results. So, by reducing the power dissipation of multiplier and adder units, we can propose a low-power MAC architecture. In this paper, first a low-power Baugh-Wooley multiplier (with a proposed 2S-T full adder design) and a conventional Baugh-Wooley multiplier (with an existing 2S-T full adder design) are analyzed using Cadence Virtuoso. The proposed full-adder-based Baugh-Wooley multiplier exhibits 32.41 microwatts of power dissipation, which is much less than the conventional Baugh-Wooley multiplier’s power consumption of 2.743 milliwatts. After multipliers, a MAC unit with a conventional multiplier is also simulated with 2.743 milliwatts and using the proposed multiplier with a significant power reduction of 0.5504 milliwatts.