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DC Field | Value | Language |
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dc.contributor.author | Mishra, Ravi Shankar | - |
dc.contributor.author | Gour, Puran | - |
dc.contributor.author | Dhariwal, Sandeep | - |
dc.contributor.author | Kumar, Gaurav | - |
dc.contributor.author | Anand, Anubhav | - |
dc.date.accessioned | 2024-01-10T10:01:11Z | - |
dc.date.available | 2024-01-10T10:01:11Z | - |
dc.date.issued | 2023-07-06 | - |
dc.identifier.isbn | 9781665456272 | - |
dc.identifier.isbn | 9781665456289 | - |
dc.identifier.uri | https://doi.org/10.1109/ICAIA57370.2023.10169461 | - |
dc.identifier.uri | http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/4758 | - |
dc.description.abstract | This research article represents low-power MAC architecture, which is one of the main building blocks of DSP processors. The MAC unit consists of three important blocks: a multiplier for multiplication, an adder for addition, and an accumulator for storing the results. So, by reducing the power dissipation of multiplier and adder units, we can propose a low-power MAC architecture. In this paper, first a low-power Baugh-Wooley multiplier (with a proposed 2S-T full adder design) and a conventional Baugh-Wooley multiplier (with an existing 2S-T full adder design) are analyzed using Cadence Virtuoso. The proposed full-adder-based Baugh-Wooley multiplier exhibits 32.41 microwatts of power dissipation, which is much less than the conventional Baugh-Wooley multiplier’s power consumption of 2.743 milliwatts. After multipliers, a MAC unit with a conventional multiplier is also simulated with 2.743 milliwatts and using the proposed multiplier with a significant power reduction of 0.5504 milliwatts. | en_US |
dc.language.iso | en | en_US |
dc.publisher | 2023 International Conference on Artificial Intelligence and Applications (ICAIA) Alliance Technology Conference (ATCON-1) | en_US |
dc.subject | Program processors | en_US |
dc.subject | Power demand | en_US |
dc.subject | Architecture | en_US |
dc.subject | Power dissipation | en_US |
dc.subject | Artificial intelligence | en_US |
dc.title | Design and Analysis of Low Power MAC for DSP Processor | en_US |
dc.type | Article | en_US |
Appears in Collections: | Journal Articles |
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