Please use this identifier to cite or link to this item:
https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/4783
Title: | High-Speed Low Power Energy Efficient 1- Trit Multiplier with Less Number of Cntfets |
Authors: | Musala, Sarada Gajula, Ramana Murthy Reddy, S V Raghu Sekhar Reddy, P Prakash |
Keywords: | CNTFETS Ternary multiplexer Hybrid design Ternary decoder |
Issue Date: | 14-Aug-2023 |
Publisher: | Multimedia Tools and Applications |
Abstract: | Ternary logic has an advantage over conventional binary logic since it uses less power and promises to take up less space on chips and in interconnects. When ternary logic is used to design multiplier circuits, they exhibit good efficiency. A device known as a carbon nanotube field-effect transistor (CNTFET) offers more benefits than a MOSFET, including low off-current characteristics like low power and good performance. In this paper, a new 1-trit multiplier design is suggested along with a comparison of four 1-trit multiplier ideas based on CNTFETs. Power, latency, PDP, and the number of transistors is compared. Power, speed, and PDP are all improved by the suggested 1-trit multiplier. There are fewer transistors required. The Cadence Virtuoso Tool simulates each of these circuits using CNTFET 32 nm technology. |
URI: | https://doi.org/10.1007/s11042-023-16403-9 http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/4783 |
ISSN: | 1573-7721 1380-7501 |
Appears in Collections: | Journal Articles |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.