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DC Field | Value | Language |
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dc.contributor.author | N. Manimekalai | - |
dc.contributor.author | A. Lelina Devi | - |
dc.date.accessioned | 2024-02-27T05:57:15Z | - |
dc.date.available | 2024-02-27T05:57:15Z | - |
dc.date.issued | 2014 | - |
dc.identifier.uri | http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/6416 | - |
dc.description.abstract | In recent years, Digitally Controlled Delay-Lines {DCDLJ Is a key block In number of app/lcattons and play the role of DAC in traditional circuits. This paper presents a totally glitch free DCDL which overcame the limitation of a NANO based DCDL using strobe control method. Using this logic, a clock Is presented, that reduces the output jitter when compared to the existing method. The existing method uses a delay control code and reduces the delay of about 40%, but it consumes more power and less is area efficient. By using strobe controlled logic, the peak to peak absolute output jitter of 70-80% was reduced. As an example application, All-Digital Spread-Spectrum Clock Generator {SSCGJ, All-Digital Phasetocked Loops {ADPLLJ, and Phase-Locked Loop {PLLJ were used. | - |
dc.publisher | Journal on Digital Signal Processing | - |
dc.title | Digitally Controlled Delay Lines Using Strobe Controlled Logic | - |
dc.vol | Vol. 2 | - |
dc.issued | No. 1 | - |
Appears in Collections: | Articles to be qced |
Files in This Item:
File | Size | Format | |
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DIGITALLY CONTROLLED DELAY LINES USING STROBE.pdf Restricted Access | 1.45 MB | Adobe PDF | View/Open Request a copy |
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