Modified Divide By 2/3 Counter Design Using Mtcmos Techniques

Abstract

In this paper, the leakage power and speed performances of extended-true single phase clock and MTCMOS using true single phase clock prescaler are investigated. Based upon this study, MTCMOS technique is implemented in True Single Phase Clock logic OFF design. By using a wired OR logic, only one transistor is used for both mode selection and counting logic systems. The working frequency of the counter is enhanced and the critical path is reduced between the OFF. Using MTCMOS technique static leakage power is reduced and the speed performances are improved. The designed counter is compared in terms of power consumption using DSCH (Digital Schematic Editor & Simulator] and Micro wind tools. Keywords: TSPC (True Single Phase Clock System), E-TSPC (Extended True Single Phase Clock System), MTCMOS Technique (Multi-thresholdCMOSJ, DFF(D-FlipFlop), Prescaler, Leakage Power, Speed Performances.