Please use this identifier to cite or link to this item: https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/6476
Title: Low Power Dissipation of Ring Counter Using Dual Sleep Transistor Approach
Authors: M. Balaji
B. Keerthana
Issue Date: 2014
Publisher: Journal on Electronics Engineering
Abstract: In CMOS [Complementary Metal Oxide Semiconductor] integrated circuits design, scaling is challenged by higher power consumption. The significant growth in power dissipation has occurred mainly due to the higher clock speeds in addition to the smaller process geometries. The transistor packaging density and functionality on a chip is improved by scaling. The speed and frequency of operation is increased due to scaling and hence higher performance is achieved. When the technology scales down, then the leakage current increases exponentially. In 90 nm and below technologies, leakage power constitutes 30-40% of total power dissipation. In this paper, a dual sleep transistor approach is used for reducing the power dissipation of ring counter circuit with minimum possible area. The simulations were done using Micro wind Layout Editor and DSCH [Digital Schematic Editor] software
URI: http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/6476
Appears in Collections:Articles to be qced

Files in This Item:
File SizeFormat 
LOW POWER DISSIPATION OF RING COUNTER USING_Pg no-14 &.pdf
  Restricted Access
3.32 MBAdobe PDFView/Open Request a copy


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.