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Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Rajashree Narendra | - |
dc.contributor.author | M. L. Sudheer | - |
dc.date.accessioned | 2024-02-27T06:00:33Z | - |
dc.date.available | 2024-02-27T06:00:33Z | - |
dc.date.issued | 2015 | - |
dc.identifier.uri | http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/6775 | - |
dc.description.abstract | Complex electronics devices are becoming more sensitive to electrostatic discharge (ESD). These components are being developed with higher density (extra memory bits per unit volume) and are becoming faster (MHz, GHz, THz, etc.). Indirect and direct air/contact discharge test has been conducted on the ALS-SDA-CPLD/FPGA trainer kit connected to the digital to analog converter (DAC) module. The Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) are found to be very ESD sensitive. The FPGA 3s50 IC was affected during the contact discharge to input pin. There was damage to the I/O pin bond pad as well as the metal top layer. There was dielectric breakdown damage observed in the CPLD 9572 IC. | - |
dc.publisher | Manufacturing Technology Today | - |
dc.title | ESD Failure Analysis of FPGA and CPLD IC | - |
dc.vol | Vol 14 | - |
dc.issued | No 4 | - |
Appears in Collections: | Articles to be qced |
Files in This Item:
File | Size | Format | |
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ESD FAILURE ANALYSIS OF FPGA AND CPLD IC.pdf Restricted Access | 2.46 MB | Adobe PDF | View/Open Request a copy |
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