Design of half adder using integrated leakage power reduction techniques

Abstract

The necessity for the development of compact, portable, and reliable electronic devices of enhanced speed and efficiency has prompted the scaling of CMOS devices to be indispensable. However, the benefit of scaling CMOS devices comes at the cost of increased leakage current in circuits. The variance in power consumption by these circuits incites detrimental impacts on the operational characteristics of the entire device. So, in this work, a novel leakage power reduction technique obtained by combining the Leakage Control Transistor (LECTOR) approach and drain gating approach is proposed. Both these subthreshold leakage minimization approaches are prominently used in Complementary Metal Oxide Semiconductor (CMOS) devices for curtailing the leakage power. The effectiveness of the proposed Integrated Drain Gating Lector (IDGL) technique in mitigating the leakage power is ascertained by designing a half adder circuit. Hence the overall leakage power is of 3.16nW & delay 69.12 µs in 180 nm technology, and in low scale technology of 90 nm the same leakage power decline to 2.19nW & delay is 65.45 µs.