Analysis of Leakage Power Suppression Technique for CMOS VCO in 45nm Technology

Abstract

This paper proposed SVL self voltage level technique for the designing of VCO (voltage controlled oscillator) circuit. Certain process parameters should be taken care of while designing of oscillator. With the scaling of transistor size power consumption in the circuit is the main reason for concern for efficient performance of the circuit designed. Having modification in the circuit with techniques SVL have not only enhanced the performance of the circuit but reduced the leakage power in the circuit designed too. By applying leakage reduction techniques in the VCO circuit, efficiency in the circuit has increased with faster speed and Lower noise. The circuits are simulated in cadence virtuoso tool at 45 nm technology.