Design and Implementation of 12 Bit Pipeline Analog to Digital Converter

Abstract

The Power dissipation and chip area of analog and mixed-signal circuits emerged has as a critical design constriction in today's VLSI design systems. This paper presents a multilevel design optimization for reducing the power dissipation and high sampling rates of a pipelined analog-to-digital converter. A 12 b 75-Msample/s analog-to-digital converter has been fabricated in a0.18-um CMOS technology. The converter uses pipelined seven stages and implements 2 hit per stage architecture. It is a fully differential analog circuit with a full-scale sinusoidal input at 20 MHz. It dissipates 3.5mW.