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DC Field | Value | Language |
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dc.contributor.author | Subodh Kumar Pandey | - |
dc.contributor.author | Sanjeev Kumar Gupta | - |
dc.date.accessioned | 2024-02-27T06:06:15Z | - |
dc.date.available | 2024-02-27T06:06:15Z | - |
dc.date.issued | 2019 | - |
dc.identifier.uri | http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/7166 | - |
dc.description.abstract | Now a days Chaos based sysLems play an imporlanl role specifically in secure communicalion and cryplography. Chaolic sys/ems have wide applications in random number genera/Ors, image encryplion, Optical secure circuits, and quanLum applicalions. The FPGA implemen/alion has certain advantages over analog one as FPGA implemenlalion of any system is having a more flexible architecture and have low cost testing cycles, nowadays more emphasis is given to realize di./Jerenl chaoLic sysLems in FPGA. This paper demonstrates the steps for FPGA implementalion of a chaotic sys/em using Euler's algorilhm. Top level, second level and third level designs are also presented. The design is implemenled using f'erilog and lested wilh Xilinx vivado v.2017.3 design suite in Artix-7 Nexys 4 DDR. Simulation results presenLed demonstraLes the liming diagram and resource uLilization. | - |
dc.publisher | Anusandhan: Rabindranath Tagore University Journal | - |
dc.title | Numerical Modelling of Chaotic System and Its FPGA Implementation | - |
dc.vol | Vol VIII | - |
dc.issued | No XV | - |
Appears in Collections: | Articles to be qced |
Files in This Item:
File | Size | Format | |
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Numerical Modelling of Chaotic System and Its FPGA Implementation.pdf Restricted Access | 2.06 MB | Adobe PDF | View/Open Request a copy |
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