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DC Field | Value | Language |
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dc.contributor.author | Gajula, Ramana Murthy | - |
dc.date.accessioned | 2023-05-24T09:27:55Z | - |
dc.date.available | 2023-05-24T09:27:55Z | - |
dc.date.issued | 2022-10-10 | - |
dc.identifier.uri | https://doi.org/10.1016/j.seta.2022.102506 | - |
dc.identifier.uri | http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/718 | - |
dc.description.abstract | This paper deals with designing an optimized hybrid Operational Transconductance Amplifier (OTA) employing a technique called source degeneration with adaptive biasing that can be used for high frequency applications. This work targets implementation of a simple technique with less number of circuit elements which reduces the die area and power consumption and gives rise to good results. The circuit has been designed to operate with a supply voltage of ±1 V along with a bias current. The linearity which is the major drawback of the conventional Complementary Metal Oxide Semiconductor (CMOS) OTA gets improved with source degeneration technique using a non-CMOS non-volatile memory (so-called memristor). The gain-bandwidth product gets improved for an 80pF load. A biquad OTA-C filter is designed and implemented utilizing the OTA designed in this work as an application example. The realization of a high pass filter has been demonstrated. All the simulations were carried out in the Cadence® Virtuoso environment using 180 nm CMOS technology. Another facet of this paper is the memristor compatibility with the CMOS process technology. | en_US |
dc.language.iso | en | en_US |
dc.title | Hybrid CMOS-Memristor based operational transconductance amplifier for high frequency applications | en_US |
dc.type | Article | en_US |
Appears in Collections: | Journal Articles |
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