An efficient design of a memristor augmented BCD to 7 segment display

Abstract

Hardware designers and engineers in today’s electronic world favour efficient alphanumeric characters display for fast developing products. Seven segment displays are widely used in most of the practical applications to provide a virtual indication of the output states of digital ICs like counters and latches. Memristor based logic is relatively a novel approach for designing digital circuits that opens a new gateway for a smaller footprint, faster operation and lower power consumption. This work mainly focuses on a unique memristor based transistor less seven segment display design and analyses the performance benchmarking with other state-of-art approaches. The findings observed shows that the proposed design performs comparatively superior in terms of size, speed and power consumption. Simulations are carried out using Cadence Virtuoso 180nm technology EDA tools. The simulation results show memristor based design achieves about 49% less area due to the reduction of circuit elements, 76.7% reduction on power consumption and 98.8% reduction on delay when compared to MOS based BCD to 7 segment displays. The observed improvement in these significant parameters demonstrate clearly the potential use of memristor based BCD to 7 segment displays in modern electronic devices.