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Please use this identifier to cite or link to this item: https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/804
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dc.contributor.authorDhariwal, Sandeep-
dc.date.accessioned2023-05-31T05:31:56Z-
dc.date.available2023-05-31T05:31:56Z-
dc.date.issued2022-01-01-
dc.identifier.urihttps://doi.org/10.23940/ijpe.22.01.p3.2229-
dc.identifier.urihttp://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/804-
dc.description.abstractLow power devices have always been important in all electronics and computer devices. In this paper, a proposed design has been implemented for the full adder circuit with significant modifications in the existing hybrid GDI (Gate Diffusion Input) based full adder. All the results are implemented using CADENCE tool at 45nm scale and 0.4V. Existing hybrid GDI based adder design delivers 7.135x10-9 watt power dissipation. The proposed hybrid GDI-PTL design delivers a significant reduction in power dissipation equal to 6.70x10-9 watt. Further, this power dissipation has been reduced to 6.55x10-9 watt by using high Vth (threshold voltage) PMOS transistor in the proposed hybrid GDI-PTL design for one-bit full adder.en_US
dc.language.isoenen_US
dc.publisherInternational Journal of Performability Engineeringen_US
dc.titleHybrid GDI PTL Full Adder: A Proposed Design for Low Power Applicationsen_US
dc.typeArticleen_US
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