Alliance University, Bengaluru
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- 6G Consumer Electronics 2
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- A Stochastic Frontier Analysis 1
- A Stochastic Low-Density Parity-Check (LDPC) decoder is a type of 5G New Radio standard LDPC decoder that uses stochastic techniques to perform decoding. Stochastic LDPC decoding with 5G NR standard typically uses an iterative process, where messages exchanged among variable nodes (VN), check nodes multiple times. Stochastic LDPC decoders are often used in scenarios where the received signal is subject to varying levels of noise. They will provide improved error correction performance compared to traditional LDPC decoders, especially when dealing with channels with varying signal-to-noise ratios in 5G networks. Using the adaptive sparse quantization kernel least mean square algorithm (SLDPC-ASQ-KLMSA), this paper proposes an area-efficient architecture design for a stochastic LDPC decoder. The LDPC code (2048, 1723) is taken from the LOGBASE-T standard and used in this study. We examine the ASQ-KLMSA connection effects. Starting with the VN. It makes checking node functioning easier and reduces inter-connect complexity by capping extrinsic message length at 2 bits. Because of the simplified check node operation in ASQ-KLMSA, the decoder nodes must exchange messages with a greater degree of accuracy. The 3–3 input grouping sub-node of the degree-6 VN was changed with an adder-based 5–1 input grouping sub-node for the (2048, 1723) code in order to get more accurate results when the check-to-variable messages aren't strong enough. A suggested decoder architecture was determined using a stochastic LDPC decoder developed for TSMC 65 nm process (2048, 1723). Bite error rate, throughput, mean square error, latency, power, and area usage are some of the metrics used to evaluate the effectiveness of the SLDPC-ASQ-KLMSA algorithm that has been suggested and implemented in Python. Thus, the proposed approach has attained 34.44%, and 38.39% low mean square error while compared with the existing methods such as higher-performance stochastic LDPC decoder architecture designed through correlation analysis (HP-SLDPC-CA), Higher Throughput and Hardware Efficient Hybrid LDPC Decoder Utilizing Bit-Serial Stochastic Updating(HLDPC-BSSU), Flexible FPGA-Based Stochastic Decoder for 5G LDPC codes (FPGA-SD-5G-LDPC), respectively. 1
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