Low Power High Speed Multiply[1]Accumulate Unit Using Partial Product Reduction Process And Dadda Multiplier

Abstract

The Multiply- Accumulation Unit (MAC) unit of low power and high speed, it accompanies dadda multiplier in its design due to its low delay compared to Wallace multiplier. Dadda multiplier is a main element for Partial Product Reduction (PPR) process to be successful in reducing the critical path delays in MAC unit, main reason for this is Dadda Multiplier that higher significance bits are not accumulated or added until PPR process of other operand begins. A clear observation on design and working of Conventional MAC results, that carry propagations contribute to delay, which is one among the trade-off’s during addition process after operands are multiplied. To overcome the path delays seen in Conventional MAC unit, a partial product reduction (PPR) process is used by integrating part of additions. Pipelining architecture is incorporated in the presented design because of its increased functionality throughput, it accumulates results in registers between logic blocks and send the results that are accumulated in a sequential order. In arithmetic pipeline, operation is broken down into sub-operations and intermediate results are stored in registers, and passed on to further stage. In fast multiplier we have 3 stages first one is Partial Product Matrix (PPR), consider we are designing a 4-bit matrix then a matrix of maximum height 4 is formed. In second step the matrix is reduced which is named as Partial Product Reduction (PPR) Process where combination of half adders and full adders are i.e., combinational circuits are used to reduce it to a height of 2 (reduced to two rows). In step three the reduced two rows are added using adders called as final addition. A small size adder is implemented in design to compensate the overflow of bits. The introduced architecture for MAC unit using Dadda Multiplier reduces delay thus can be used in DSP application and real-time applications for faster computational results. This work involves architecture simulation results of power consumption and circuit area under same timing constraints compared with other architecture results.