Sense-Amplifier-Based Flip-Flop In 45Nm Mtcmos with Reduction In Power Consumption and Delay

Abstract

This project proposes a novel sense amplifier-based flip-flop (SAFF) circuit designed for low-power and high-speed operation in 45nm multi-threshold CMOS (MTCMOS) technology. The design incorporates insights from existing research to achieve significant reductions in both power consumption and propagation delay compared to conventional SAFFs and master-slave flip-flops (MSFFs). The key innovations lie in the improved sense amplifier and latch stage design, which facilitates efficient amplification and data storage with lower power consumption and faster operation. Additionally, a conditional cut-off strategy is employed within the latch stage to eliminate glitches and ensure stable performance. MTCMOS optimization is strategically utilized to minimize leakage current during inactive periods, leading to substantial power savings. Finally, the design allows for reliable operation at lower supply voltages through MTCMOS optimization, offering additional power efficiency benefits. The project aims to achieve significant reductions in both power consumption and propagation delay, while also achieving an improved power-delay product compared to conventional SAFFs and MSFFs. Additionally, the design strives to maintain a competitive area footprint similar to conventional SAFFs. Simulations using tools like Cadence Virtuoso will be conducted to verify functionality and measure performance metrics. Layout design and post-layout simulations will also be performed to confirm functionality and performance on a 45nm standard cell library. Area optimization may be further explored to further reduce the footprint while maintaining performance targets.