Reconfigurable Pulsed Latches For Enhanced Reliability In Low-Power Sequential Circuits

Abstract

As low-electricity ASIC designs continue to evolve, pulsed latches have emerged as a promising alternative to standard flip-flops, offering high performance and reduced area and energy consumption. However, despite their advantages, the impact of PVT variations on the reliability of pulsed latches circuits remains a critical concern with limited research attention. This project addresses this gap by conducting a comprehensive analysis of PVT variations in a 45nm technology node, focusing on both the pulser and latch components within pulsed latches circuits. The project includes the design of a pulse generator optimized for minimum energy consumption while enhancing circuit dependability. The designs are evaluated against existing methodologies in terms of area, power, and delay metrics to demonstrate the improvements achieved. The proposed designs are implemented using the Multisim tool with stipulated specifications. Furthermore, a novel shift register design leveraging digital pulsed latches is introduced to enhance area and power efficiency. By utilizing multiple non-overlapping delayed pulsed clock signals and grouping latches into sub shifter registers, significant savings in area and energy consumption are achieved compared to traditional flip-flop-based shift registers. Overall, this project contributes to the development of reconfigurable latch designs, offering adaptability and customization options essential for managing data in compact electronic environments with varying operational requirements.