Analyzing the Low Power Techniques In Sram Cells At 45Nm Node Technology

Abstract

This paper presents Gated Vdd and MTCMOS techniques to achieve low power from the simulated static random-access memory (SRAM) cells. These techniques are implemented on 4 T, 5 T and 6 T memory circuits based on CMOS logic. A significant research work is already in progress in the field of electronics embedded with memory with low power technology for system on chip (SoC). One of the most popular memory cells is 6 T SRAM for microprocessor and micro controller architectures for low power applications. This research paper discusses CMOS based SRAM circuits and the parameters considered are power dissipation and delay. Along with 6 T, the other two memory cells (4 T and 5 T) are also simulated with modifications of the low power techniques. Delay and power dissipation are analyzed for the conventional designs and modified designs with low power methodology. Low power techniques like Gated Vdd and MTCMOS (Multi Threshold CMOS), have been instrumental in reducing the power consumption at 45nm node technology. All the designs are simulated and compared to ponder on best outcome. Comparative analysis shows that the MTCMOS based SRAM cells (specially 6 T) represent overall a better choice for reduced power dissipation and delay. © 2024 IEEE.