Comparative Analysis of Low Power Sram Cells Using Gated Vdd and Mtcmos Techniques

Abstract

In this paper, Gated Vdd and MTCMOS techniques are proposed to get low power from the simulated SRAM cells considering 4T, 5T and 6T circuits based on CMOS logic. In the present time, huge evolutions have been made in the field of electronics embedded with memory technology for organized working. Out of many memory cells, the most popular is MOS based SRAM (Static Random-Access Memory), especially for microprocessor and microcontroller architectures. This paper discusses SRAM circuits with parameters of power dissipation and delay. In this paper, SRAM cell designs with low power techniques have been analyzed for delay and power dissipation. Low power techniques like Gated Vdd and MTCMOS (Multi Threshold CMOS), have been applied to reduce the power consumed by the SRAM cells. These designs are related to an existing 6T SRAM cell. Results show that the MTCMOS-based SRAM cells represent better choice for reduced power dissipation and delays. © 2024 Nova Science Publishers, Inc.