Datapath Design and Power Optimization in High Speed Core

Abstract

In today’s high performance advanced VLSI circuit design including most semicustom designs adapt efficient utilization of circuit resources with better productivity offering a good layout density and high performances with optimum resources in submicron designs. The major focus of this work is to optimize the Functional Unit Block which is part of a processor in terms of timing, power and area. Datapath design methodology along with the enhancement of the existing design technology and optimization methods, is used to deliver a quality design and this work also proposes various logical optimization, RTL changes, placement, routing optimization techniques to meet the specifications in terms of power, timing. Datapath designing is a method where the logic synthesis of the design is done manually without any tool based, approach, to give more control over the design. The major focus of the work is to understand the functionality of the functional unit block, and implement the best suitable power optimization methodologies that include sizing sequential cells, Latch conversions, Redundant buffer removal, Clock gating and buffer merging to optimize the FUB in terms of timing and power to meet the specifications and also the quality. A power gain of 0.4% is claimed in this paper.