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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Joseph, J Armstrong | - |
dc.contributor.author | Korah, Reeba | - |
dc.contributor.author | Salivahanan | - |
dc.date.accessioned | 2023-12-06T10:14:27Z | - |
dc.date.available | 2023-12-06T10:14:27Z | - |
dc.date.issued | 2015 | - |
dc.identifier.citation | Vol. 10, No. 92; pp. 149-154 | en_US |
dc.identifier.issn | 0973-4562 | - |
dc.identifier.issn | 0973-9769 | - |
dc.identifier.uri | https://www.ripublication.com/ijaerspl2015/ijaer10n92spl_23.pdf | - |
dc.identifier.uri | http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/2171 | - |
dc.description.abstract | Network based Intrusion detection system are passive and non-intrusive devices that are listen on network without interfering network operations and monitors as security from attacks. Regular expressions have been adopted in pattern matching to detect intrusion over network. Reconfigurable hardware such as FPGA devices provides to achieve high performance in terms of processing time. In this work, matching modules functionality described through Snort rule based option controlled by Finite sate machine in Dynamic Reconfigurable Architecture using Verilog HDL. The speedups achieve by minimize the reconfiguration latencies, reducing memory access time and simulation time are analyzed using Xilinx ISE design suite13.2 tool. The processing time for a single packet is 37 ?S. © 2015, Research India Publications. All rights reserved. | en_US |
dc.language.iso | en | en_US |
dc.publisher | International Journal of Applied Engineering Research | en_US |
dc.subject | Dynamic Reconfigurable Architecture | en_US |
dc.subject | FPGA | en_US |
dc.subject | Network IDS | en_US |
dc.subject | Potential exploitation of parallelism | en_US |
dc.subject | Snort rules | en_US |
dc.title | A Network Based Intrusion Detection System In Dynamic Reconfigurable Architecture | en_US |
dc.type | Article | en_US |
Appears in Collections: | Journal Articles |
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