Please use this identifier to cite or link to this item: https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/2285
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dc.contributor.authorGuturu, Sahith-
dc.contributor.authorUppugunduru, Anil Kumar-
dc.contributor.authorThota, Sridhar-
dc.contributor.authorAhmed, Syed Ershad-
dc.date.accessioned2023-12-09T08:56:05Z-
dc.date.available2023-12-09T08:56:05Z-
dc.date.issued2021-
dc.identifier.citationpp. 79-83en_US
dc.identifier.isbn9781728187532-
dc.identifier.isbn9781665416184-
dc.identifier.urihttps://doi.org/10.1109/iSES52644.2021.00029-
dc.identifier.urihttp://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/2285-
dc.description.abstractApproximate Computing is a paradigm shift to meet the future demands of compute-intensive tasks such as media processing, data mining, and recognition. These applications can tolerate errors up to a specific limit. In such applications, addition is one unit that is power-hungry by approximating the adder savings in area, power, and delay can be achieved. This paper presents a technique of approximating the least significant portion in an adder while improvement in accuracy is achieved using OR-based logic. This results in a reduction of area and power without significant compromise in accuracy. Based on the approximation region, we propose three designs with a tradeoff in computation complexity and accuracy. The results prove the efficacy of the proposed designs and an improvement up to 51.39%, improvement in power w.r.t existing designs. © 2021 IEEE.All rights reserved.en_US
dc.language.isoenen_US
dc.publisher2021 IEEE International Symposium on Smart Electronic Systems (iSES), iSES 2021en_US
dc.subjectApproximate Adderen_US
dc.subjectApproximate Computingen_US
dc.subjectImage Sharpeningen_US
dc.subjectLow Poweren_US
dc.titlePower-Efficient Mloa For Error Resilient Applicationsen_US
dc.typeArticleen_US
Appears in Collections:Conference Papers

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