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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Nithya, N | - |
dc.contributor.author | Itapu, Srikanth | - |
dc.date.accessioned | 2024-01-10T10:04:50Z | - |
dc.date.available | 2024-01-10T10:04:50Z | - |
dc.date.issued | 2023-09-04 | - |
dc.identifier.isbn | 9798350334395 | - |
dc.identifier.isbn | 9798350334401 | - |
dc.identifier.issn | 2766-2101 | - |
dc.identifier.issn | 2334-0940 | - |
dc.identifier.uri | https://doi.org/10.1109/CONECCT57959.2023.10234778 | - |
dc.identifier.uri | http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/4760 | - |
dc.description.abstract | This paper’s major objective is to suggest a creative strategy for improving CPU performance in real-time operating systems by developing a fresh way for the round-robin CPU scheduling algorithm. Round-robin and priority scheduling methods are combined in the proposed method to create the Priority based Round-Robin CPU Scheduling algorithm. This algorithm addresses the starvation prevention issue present in round-robin scheduling while including the benefits of priority ordering. By giving different priorities to processes, it also adds the idea of ageing. Due to its flaws, such as high context transition rates, prolonged wait times, lengthy responses, prolonged turnaround times, and limited throughput, the current round-robin CPU scheduling algorithms are not suited for real-time operating systems. These restrictions are removed by the suggested approach, which also fixes the round-robin algorithm’s problems. The study compares the proposed algorithm with the existing round-robin scheduling method based on a number of variables, including time quantum, average waiting time, average turnaround time, and number of context shifts, in order to assess its efficacy. Although the semiconductor industry has a lot of interest in CPU-GPU multi-core research, the problems raised in the literature have not yet been solved. This project focuses on the creation of a novel heterogeneous crossbar style network-on-chip (NoC) that connects heterogeneous CPU-GPU processors in order to overcome these issues. | en_US |
dc.language.iso | en | en_US |
dc.publisher | 2023 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) | en_US |
dc.subject | Job shop scheduling | en_US |
dc.subject | Program processors | en_US |
dc.subject | Scheduling algorithms | en_US |
dc.subject | Multicore processing | en_US |
dc.subject | Operating systems | en_US |
dc.subject | Network-on-chip | en_US |
dc.subject | Computer architecture | en_US |
dc.title | Design Of Low Area Interconnect Architecture for CPU-GPU Network-On-Chips (NoCs) | en_US |
dc.type | Article | en_US |
Appears in Collections: | Journal Articles |
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