Please use this identifier to cite or link to this item: https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/6416
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dc.contributor.authorN. Manimekalai-
dc.contributor.authorA. Lelina Devi-
dc.date.accessioned2024-02-27T05:57:15Z-
dc.date.available2024-02-27T05:57:15Z-
dc.date.issued2014-
dc.identifier.urihttp://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/6416-
dc.description.abstractIn recent years, Digitally Controlled Delay-Lines {DCDLJ Is a key block In number of app/lcattons and play the role of DAC in traditional circuits. This paper presents a totally glitch free DCDL which overcame the limitation of a NANO based DCDL using strobe control method. Using this logic, a clock Is presented, that reduces the output jitter when compared to the existing method. The existing method uses a delay control code and reduces the delay of about 40%, but it consumes more power and less is area efficient. By using strobe controlled logic, the peak to peak absolute output jitter of 70-80% was reduced. As an example application, All-Digital Spread-Spectrum Clock Generator {SSCGJ, All-Digital Phasetocked Loops {ADPLLJ, and Phase-Locked Loop {PLLJ were used.-
dc.publisherJournal on Digital Signal Processing-
dc.titleDigitally Controlled Delay Lines Using Strobe Controlled Logic-
dc.volVol. 2-
dc.issuedNo. 1-
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