Power Efficient Implementation of Least Mean Square Algorithm Based Fir Filter Design Using FPGA

Abstract

This paper describes a high-speed and low-complexity Implementation of FIR FIiter using Least Mean Square Technique. Multiplex-Based Zero-Adaptation-Delay Structure and Two Adaptation Delay Structure for a direct LMS adaptive FIR filter is proposed. This paper describes that the proposed adder technique provides much faster convergence and lower complexity for obtaining lower area, power dissipation, high speed and lower propagation delay. The multiplexer circuits were schematized using the DSCH2 schematic design tool, and their layouts were generated with the Micro wind to VLSI layout CAD tool. Th.e parameter analyses were performed with a BSIM4 analyzer. The proposed multiplex -based filters are used to carry save adder as well as other existing adder circuit in terms of power dissipation, propagation delay, latency, and throughput. Our proposed structure Involves minimum power. Finally the simulations are done using Xilinx /SE design suite to get power and implemented on Spartan 3E FPGA kit.