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DC Field | Value | Language |
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dc.contributor.author | A G. Sasikala | - |
dc.contributor.author | S. Maragatharaj | - |
dc.date.accessioned | 2024-02-27T05:57:33Z | - |
dc.date.available | 2024-02-27T05:57:33Z | - |
dc.date.issued | 2014 | - |
dc.identifier.uri | http://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/6477 | - |
dc.description.abstract | Quantum Dot Cellular Automata (QCA) is an emerging nanotechnology in the field of Quantum electronics for low power consumption and high speed of operational phenomenon. Such type of circuit can be used in many digital applications where CMOS [Complementary Metal Oxide Semiconductor] circuits cannot be used due to high leakage and low switching speed. Also, reversible logic is becoming a more and more prominent technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. Reversibility plays an important role when energy efficient computations are considered. By combining both of these low power and area efficient QCA technologies, the author can make a new generation low power system. In this paper, reversible eight-bit parallel binary adder/Sub tractor using QCA has been proposed. This method reduces the total area used compared to the normal CMOS based structures and reduces power dissipation by using reversible logic gates. | - |
dc.publisher | I-manager's Journal on Electronics Engineering | - |
dc.title | QCA Based Low Power Parallel Binary Adder/Subtractor Using Reversible Logic Gates | - |
dc.vol | Vol. 4 | - |
dc.issued | No. 3 | - |
Appears in Collections: | Articles to be qced |
Files in This Item:
File | Size | Format | |
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QCA BASED LOW POWER PARALLEL BINARY ADDER.pdf Restricted Access | 3.07 MB | Adobe PDF | View/Open Request a copy |
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