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Please use this identifier to cite or link to this item: https://gnanaganga.inflibnet.ac.in:8443/jspui/handle/123456789/6483
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dc.contributor.authorM. Bharathi-
dc.contributor.authorNeelima Koppala-
dc.date.accessioned2024-02-27T05:57:34Z-
dc.date.available2024-02-27T05:57:34Z-
dc.date.issued2014-
dc.identifier.urihttp://gnanaganga.inflibnet.ac.in:8080/jspui/handle/123456789/6483-
dc.description.abstractThe multiplier in any arithmetic unit dissipates significant amount of energy as large number of computations are required ifthe number of bits in the design Increase. Thus, if efficient reversible logic is used, then the power consumption can be reduced drastically as the Information bits are not lost In case of reversible computation.-
dc.publisherJournal on Embedded Systems-
dc.title2-Bit Ex-Or Link Based Reversible Multiplier for Low Power DSP Applications-
dc.volVol. 3-
dc.issuedNo. 1-
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