Effect of coupling capacitor in onchip interconnects of driver – receiver circuits

Abstract

The demand from the consumers and the market are continuously increasing for portable and fast responding devices, then the pressure on VLSI designers community persistent continuously. Though the Moore’s law predicts doubling of transistor density for every eighteen months the challenge every day on VLSI industry is continuous. Earlier the onchip interconnects were not considered for the vital metrics like power and delay, but it cannot be neglected further. Any interconnect does have the effect of Resistance (R), Inductance (L)and Capacitance (C). In most of the cases RC effect will be considered only in specific cases the effect of Inductance considered. In this work the effect of capacitance considered for both single interconnect and bus architecture and two designs say scheme A and scheme B are proposed. The scheme A based on only analog, and scheme B designed to respond both digital and analog that is for mixed signals. Scheme A is chosen since it is performing better in terms of power consumption and power delay product.